A DRAM consists of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and a field effect transistor, hereinafter referred to as an access transistor, for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Therefore, the memory has two states; often thought of as the true logic state and the complementary logic state. There are two options available in a DRAM memory: a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is transmitted on signal lines, also called digit lines, to and from the Input/Output lines, hereinafter known as I/O lines, through field effect transistors used as switching devices and called decode transistors. For each bit of data stored, its true logic state is available at an I/O line and its complementary logic state is available at a line designated I/O*. For purposes or this discussion, I/O and I/O* lines are often referred to as just I/O lines. Thus, each cell has two digit lines, referred to as digit line pairs.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows and columns and a memory cell is associated with each intersection. In order to read from or write to a cell, the particular cell in question must be selected, also called addressed. The address for the selected cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a wordline in response to the row address. The selected wordline activates the access transistor for each of the memory cells in electrical communication with the selected wordline. Next the column decoder activates a column decoder output in response to the column address. The active column decoder output selects the desired digit line pair. For a read operation the selected wordline activates the access transistors for a given row address, and data is latched to the digit line pairs. The column decoder output selects and activates the decode transistors such that the data is transferred from the selected digit line pair to the I/O lines.
The row decoder comprises decode circuitry for determining which wordline is selected for a desired address and for determining which wordlines are non-selected. The row decoder also comprises driver circuitry for driving the selected and the non-selected wordlines to potentials having active and inactive logic states respectively. The active wordline has a potential capable of activating the access transistors in electrical communication with the active wordline and the inactive wordline has a potential capable of deactivating the access transistors in electrical communication with the non-selected wordlines. For this discussion the selected wordline will have a high potential and the non-selected wordlines will have low potentials.
Typically the decode circuitry comprises a primary decoder and a secondary decoder for generating a primary select signal, S.sub.1 *, and at least one secondary select signal, S.sub.2, respectively. The asterisk indicates that the signal is active low. The primary and secondary select signals are used as inputs to a driver portion of the row decoder. The driver portion typically comprises an inverter portion and a latch portion. The primary select signal is typically inverted to the wordline by the inverter portion, and the secondary select signal regulates the switching of the primary select signal to the inverter portion. The latch portion latches a nonselected wordline to the inactive logic state.
Typical decoder circuitries can comprise either MOS decodes utilizing NAND circuitry or NOR circuitry, or tree decode circuitry. FIGS. 1, 2 and 3 are examples of a portion of the NAND, NOR, and tree decode circuitries respectively. The decode circuitries of the row decoder provide predecoded addresses to select the driver portion of the row decoder circuit. MOS decode circuitry provides predecode signals comprising the primary select signal, S.sub.1 *, and the secondary select signal, S.sub.2. Although the specific decode circuitry determining the values of S.sub.1 * and S.sub.2 can vary, the variations are well known in the art. FIGS. 1-3 have been included to provide examples of portions of possible decode circuitries. FIG. 1 is an example of a portion of a CMOS NAND decode circuit wherein each of the secondary select signals, S.sub.2A, S.sub.2B, S.sub.2C and S.sub.2D, is a one of four decode having four phases, and wherein S.sub.1 * (not shown) comes from a one of 64 CMOS NAND decode used to decode 256 wordlines. FIG. 2 is an example of a portion of a CMOS NOR decode circuit wherein each of the primary select signals, S.sub.1A *, S.sub.1B *, S.sub.1C * and S.sub.1D *, is a one of four decode using four phases, and wherein secondary select signal S.sub.2, (not shown), comes from a one of 64 CMOS NOR decode used to decode 256 wordlines.
In the circuits of FIGS. 1 and 2, the secondary select signal controls the activation of a single pass transistor. The decode circuitry may employ the tree decode configuration wherein a plurality of serially connected pass transistors are activated in order to drive the selected wordline to a high logic level. In the example depicted by FIG. 3 predecode address signals activate three serially connected pass transistors. For example if predetermined address signals RA56(0), RA34(0), and RA12(1) are high and the remaining predecode addresses are low, transistors 1,2, and 3 are activated providing an electrical path between points 4 and 5. These decode circuitries are well known to those skilled in the art.
FIG. 4 is a simplified schematic of the driver circuit of the related art. Each wordline in the array has a similar driver circuit. In FIG. 4, a MOS decode has been utilized to provide a primary select signal S.sub.1 * at primary select node 4 and a secondary select signal S.sub.2 at secondary select node 6. The select signals S.sub.1 * and S.sub.2 control the potential of the wordline 8. The primary select signal is transmitted through NMOS transistor 9 and continually gated transistor 10 to an inverter/latch portion 11 when the secondary select signal is high. When select signal S.sub.2 is high, NMOS transistor 9 activates and the select signal on S.sub.1 * is inverted to the wordline 8.
FIG. 5 is a simplified schematic of a portion of the decode circuitry of a typical row decoder of the related art. Primary select signals S.sub.1 * and S.sub.1 '* and secondary select signals S.sub.2 and S.sub.2 ' are generated by decode circuitry (not shown). The purpose of this discussion is to provide an understanding of the final mechanism for activating and deactivating the wordlines and to provide an understanding of the relationship between the select signals and the driver circuit. At the onset of each read or write cycle, all of the wordlines are typically reset to a low potential. In this case, select signals S.sub.1 *, S.sub.1 '*, S.sub.2, and S.sub.2 ' have a high potential which take the potentials of the wordlines 12, 14, 16, and 18 low.
During the selection of a wordline the secondary select signals go low except for the secondary select signal which activates the pass transistor in electrical communication with the selected wordline. All of the primary select signals remain high except for the primary select signal which must be inverted to the selected wordline.
Still referring to FIG. 5, assume the desired address selects wordline 14. In this case select signal S.sub.2 goes low and select signal S.sub.2 ' is high; and select signal S.sub.1 '* goes low, and select signals S.sub.1 * is high. The low select signal S.sub.1 '* is inverted to wordline 14 through activated transistor 22. Although transistors 21 and 23 are deactivated the wordlines 12 and 16 remain at the initial low potential due to a latching of the low potential by the inverter/latch portion 11 of the driver circuits. Wordline 18 is driven low when the high potential of S.sub.1 * is driven through activated transistor 24 and inverted to wordline 18.
FIG. 6 is exemplary of a driver portion of a row decoder circuit wherein the decode portion is implemented with tree decode circuitry having a plurality of pass transistors 25.
Serial nodes 26 and 27 tend to float to unknown potentials between cycles of cell selection. Since it is important to know the potential of serial nodes 26 and 27 the serial nodes 26 and 27 are typically reset to a known potential prior to the selection of the active wordline. During reset transistors 25 are actuated thereby precharging the serial nodes 26 and 27 to a high potential. Initial precharging presents a problem since there is a significant power consumption associated with precharging all of the serial nodes at the onset of each cycle.
In some circuits there have been problems with latch up. Latch up occurs when node 40 in FIGS. 4 and 6 has latched to the high supply potential through a transistor component (not shown) of the driver circuit. Latch up occurs when the potential of node 40 is greater than the supply potential, V.sub.ccp. This can occur during power up when the supply potential is increasing. In order to eliminate latch up, a transistor device 10 is continually gated by a V.sub.ccp supply potential as shown in FIGS. 4 and 6. Transistor device 10 keeps the potential at node 40 less than the supply potential as long as the potentials at nodes 42 and 27 are less than the supply potential. Therefore, as long as the potentials at nodes 42 and 27 are less than V.sub.ccp, the pan will not latch up since the n-well of the transistor component of the driver circuit will never be forward biased. The function of the continually gated device will become clear when analyzed with respect to subsequent schematics of the present invention.
V.sub.ccp is a high voltage pump potential typically equal to the supply potential, V.sub.cc, of the memory device plus a threshold voltage, V.sub.t, of the access transistor, V.sub.cc +V.sub.t equals V.sub.ccp. The threshold voltage of the access transistor is the potential that must be overcome in order for the access transistor to conduct current.
In order to conserve power, supply potentials of many memory devices have been decreased from the typical 5 volt V.sub.cc. A low supply voltage of 3.3 volts is increasingly replacing the 5 volt operation. There is a disadvantage associated with the lower supply potentials. Often the potentials driven to a node are marginal. They often do not meet the minimum low potentials for a high logic state. Thus, circuits can experience erroneous outputs potentials. For example, in FIG. 6 when the supply voltage is approximately 3 volts, the select signal on S.sub.1 * may be 3 volts. Considering that the NMOS transistor doesn't pass high potentials with minimal loss, we must expect a threshold voltage drop across the NMOS transistors 25. The input voltage to the inverter/latch 11, FIGS. 4-6, may drop from 3 volts to 2 volts due to the threshold loss. There exists the increased probability that the inverter/latch 11 will see the 2 volts as a low logic state rather than the high logic state desired, or that the threshold voltage loss will be greater thereby decreasing the potential at the input of the inverter/latch. A need therefore exists to provide a row decoder that consistently drives the wordline to the inactive low state for a high primary select signal regardless of the supply potential used. Therefore, memory device circuits need to be redesigned in order to successfully drive wordlines to low logic levels for circuits utilizing supply potentials less than the typical 5 volts.
Further understanding of the DRAM circuitry can be gleaned from the DRAM DATA BOOK, 1992, published by Micron Technology and herein incorporated by reference.